hello,
I'm trying to port linux into Mitac Mio P550.
http://www.mio-tech.com/gps-navigation-products-p550-overview.htm
I am studying the source code of Haret and I am compiling new kernels of
linux but I can`t boot the linux.
you can see my problem in the web site:
http://www.youtube.com/watch?v=iICAMzp4Qt0
I'm using the s3c2440a datasheet. I'm using haret in the dump of the memory
registries and others functions.
My actuality information is:
I/O PORT CONTROL REGISTER
PORT A CONTROL REGISTERS(GPACON, GPADAT)
GPACON Bit Description
GPA24 reserved
GPA23 reserved
GPA22 nFCE
GPA21 nRSTOUT
GPA20 nFRE
GPA19 nFWE
GPA18 ALE
GPA17 CLE
GPA16 Output
GPA15 Output
GPA14 Output
GPA13 nGCS[2]
GPA12 Output
GPA11 Output
GPA10 ADDR25
GPA9 ADDR24
GPA8 Output
GPA7 Output
GPA6 Output
GPA5 Output
GPA4 Output
GPA3 Output
GPA2 ADDR17
GPA1 ADDR16
GPA0 Output
PORT B CONTROL REGISTERS(GPBCON, GPBDAT, GPBUP)
PBCON Bit Description
GPB10 Output
GPB9 Output
GPB8 Input
GPB7 Output
GPB6 Output
GPB5 Output
GPB4 Output
GPB3 Output
GPB2 Output
GPB1 Output
GPB0 TOUT0
PORT C CONTROL REGISTERS(GPCCON, GPCDAT, GPCUP)
GPCCON Bit Description
GPC15 [31:30] VD[7]
GPC14 [29:28] VD[6]
GPC13 [27:26] VD[5]
GPC12 [25:24] VD[4]
GPC11 [23:22] VD[3]
GPC10 [21:20] Output
GPC9 [19:18] Output
GPC8 [17:16] Output
GPC7 [15:14] Output
GPC6 [13:12] Output
GPC5 [11:10] Output
GPC4 [9:8] VM
GPC3 [7:6] VFRAME
GPC2 [5:4] VLINE
GPC1 [3:2] VCLK
GPC0 [1:0] Output
PORT D CONTROL REGISTERS(GPDCON, GPDDAT, GPDUP)
GPDCON Bit Description
GPD15 [31:30] VD[23]
GPD14 [29:28] VD[22]
GPD13 [27:26] VD[21]
GPD12 [25:24] VD[20]
GPD11 [23:22] VD[19]
GPD10 [21:20] Output
GPD9 [19:18] Output
GPD8 [17:16] Output
GPD7 [15:14] VD[15]
GPD6 [13:12] VD[14]
GPD5 [11:10] VD[13]
GPD4 [9:8] VD[12]
GPD3 [7:6] VD[11]
GPD2 [5:4] VD[10]
GPD1 [3:2] Output
GPD0 [1:0] Output
PORT E CONTROL REGISTERS(GPECON, GPEDAT, GPEUP)
GPECON Bit Description
GPE15 [31:30] Input
GPE14 [29:28] Input
GPE13 [27:26] Output
GPE12 [25:24] Output
GPE11 [23:22] Output
GPE10 [21:20] SDDAT3
GPE9 [19:18] SDDAT2
GPE8 [17:16] SDDAT1
GPE7 [15:14] SDDAT0
GPE6 [13:12] SDCMD
GPE5 [11:10] SDCLK
GPE4 [9:8] AC_SDATA_OUT
GPE3 [7:6] AC_SDATA_IN
GPE2 [5:4] Output
GPE1 [3:2] AC_BIT_CLK
GPE0 [1:0] AC_SYNC
PORT F CONTROL REGISTERS(GPFCON, GPFDAT)
GPFCON Bit Description
GPF7 [15:14] EINT[7]
GPF6 [13:12] Input
GPF5 [11:10] EINT[5]
GPF4 [9:8] EINT[4]
GPF3 [7:6] EINT[3]
GPF2 [5:4] EINT[2]
GPF1 [3:2] EINT[1]
GPF0 [1:0] EINT[0]
PORT G CONTROL REGISTERS(GPGCON, GPGDAT)
GPGCON Bit Description
GPG15* [31:30] Input
GPG14* [29:28] Input
GPG13* [27:26] Input
GPG12 [25:24] Input
GPG11 [23:22] Output
GPG10 [21:20] Input
GPG9 [19:18] Input
GPG8 [17:16] Input
GPG7 [15:14] EINT[15]
GPG6 [13:12] EINT[14]
GPG5 [11:10] EINT[13]
GPG4 [9:8] EINT[12]
GPG3 [7:6] EINT[11]
GPG2 [5:4] EINT[10]
GPG1 [3:2] EINT[9]
GPG0 [1:0] Output
PORT H CONTROL REGISTERS(GPHCON, GPHDAT)
GPHCON Bit Description
GPH10 [21:20] CLKOUT1
GPH9 [19:18] CLKOUT0
GPH8 [17:16] Output
GPH7 [15:14] RXD[2]
GPH6 [13:12] TXD[2]
GPH5 [11:10] Output
GPH4 [9:8] Output
GPH3 [7:6] RXD[0]
GPH2 [5:4] TXD[0]
GPH1 [3:2] nRTS0
GPH0 [1:0] nCTS0
PORT J CONTROL REGISTERS(GPJCON, GPJDAT)
GPJCON Bit Description
GPJ12 [25:24] Output
GPJ11 [23:22] Output
GPJ10 [21:20] Output
GPJ9 [19:18] Output
GPJ8 [17:16] Output
GPJ7 [15:14] Output
GPJ6 [13:12] Output
GPJ5 [11:10] Output
GPJ4 [9:8] Output
GPJ3 [7:6] Output
GPJ2 [5:4] Output
GPJ1 [3:2] Output
GPJ0 [1:0] Output
Memory Dump
-----------------------------------------------
SROM (NGCS0)
-----------------------------------------------
START ADDRESS = 00000000
END ADDRESS = 01f00000
SIZE = 32Mb
NGCS0 BOOT INTERNAL = 00000000 -> 1Mb
-----------------------------------------------
SROM (NGCS1)
-----------------------------------------------
START ADDRESS = 08000000
END ADDRESS = 09f00000
SIZE = 32Mb
-----------------------------------------------
SROM (NGCS2)
-----------------------------------------------
START ADDRESS = 10000000
END ADDRESS = 11f00000
SIZE = 32Mb
-----------------------------------------------
SROM (NGCS3)
-----------------------------------------------
START ADDRESS = 18000000
END ADDRESS = 19f00000
SIZE = 32Mb
-----------------------------------------------
SROM (NGCS4)
-----------------------------------------------
START ADDRESS = 20000000
END ADDRESS = 21f00000
SIZE = 32Mb
-----------------------------------------------
SROM (NGCS5)
-----------------------------------------------
START ADDRESS = 28000000
END ADDRESS = 29f00000
SIZE = 32Mb
-----------------------------------------------
SROM (NGCS6)
-----------------------------------------------
START ADDRESS = 30000000
END ADDRESS = 33f00000
SIZE = 64Mb
-----------------------------------------------
SROM (NGCS7) -> No DUMP
-----------------------------------------------
The source code of linux kernel in the NAND Function is:
static struct s3c2410_uartcfg miop550_uartcfgs[] = {
[0] = {
.hwport = 0,
.flags = 0,
.ucon = 0x3c5,
.ulcon = 0x03,
.ufcon = 0x51,
.clocks = miop550_serial_clocks,
.clocks_size = ARRAY_SIZE(miop550_serial_clocks),
},
[1] = {
.hwport = 1,
.flags = 0,
.ucon = 0x3c5,
.ulcon = 0x03,
.ufcon = 0x00,
.clocks = miop550_serial_clocks,
.clocks_size = ARRAY_SIZE(miop550_serial_clocks),
},
/* IR port */
[2] = {
.hwport = 2,
.uart_flags = UPF_CONS_FLOW,
.ucon = 0x3c5,
.ulcon = 0x43,
.ufcon = 0x51,
.clocks = miop550_serial_clocks,
.clocks_size = ARRAY_SIZE(miop550_serial_clocks),
}
};
/* framebuffer lcd controller information */
// Informacion LCDCON1 MIOP550 usando Haret ( PDUMP 0x4D000000 = 04400A79)
// ENVID [BIT 0] = 1 ( Enable the video output and the LCD control signal)
// BPPMODE [BIT 4:1] = 1100 ( 16 BPP FOR TFT )
// PNRMODE [BIT 6:5] = 11 ( TFT LCD PANEL )
// MMODE [BIT 7] = 0 ( Each Frame )
// CLKVAL [BIT 17:8] = 0...1010 = 0A (hex)
// LINECNT [BIT 27:18] = 0100010000 = 110 (hex)
static struct s3c2410fb_mach_info miop550_lcdcfg __initdata = {
.regs = {
.lcdcon1 = S3C2410_LCDCON1_TFT16BPP |
S3C2410_LCDCON1_TFT |
S3C2410_LCDCON1_CLKVAL(0x0A),
S3C2410_LCDCON1_CLKVAL(0x0C),
S3C2410_LCDCON1_CLKVAL(0x04),
.lcdcon2 = S3C2410_LCDCON2_VBPD(1) |
S3C2410_LCDCON2_LINEVAL(319) |
S3C2410_LCDCON2_VFPD(3) |
S3C2410_LCDCON2_VSPW(0),
.lcdcon3 = S3C2410_LCDCON3_HBPD(17) |
S3C2410_LCDCON3_HOZVAL(239) |
S3C2410_LCDCON3_HFPD(9),
.lcdcon4 = S3C2410_LCDCON4_MVAL(0) |
S3C2410_LCDCON4_HSPW(4),
.lcdcon5= S3C2410_LCDCON5_FRM565 |
S3C2410_LCDCON5_INVVLINE |
S3C2410_LCDCON5_INVVFRAME |
S3C2410_LCDCON5_HWSWP,
},
.lpcsel = 0xf82,
//.lpcsel = 0xCE6,
// .lpcsel = ((0xCE6) & ~7) | 1<<4,
.type = S3C2410_LCDCON1_TFT16BPP,
.gpccon = 0xaa9556a9,
// .gpccon_mask= 0xffffffff,
.gpccon_mask = 0xffc003fc,
.gpcup = 0x0000ffff,
.gpcup_mask = 0xffffffff,
.gpdcon = 0xaa95aaa5,
// .gpdcon_mask= 0xffffffff,
.gpdcon_mask = 0xffc0fff0,
.gpdup = 0x0000ffff,
.gpdup_mask = 0xffffffff,
.fixed_syncs = 1,
.width = 240,
.height = 320,
.xres = {
.min = 240,
.max = 240,
.defval = 240,
},
.yres = {
.max = 320,
.min = 320,
.defval = 320,
},
.bpp = {
.min = 16,
.max = 16,
.defval = 16,
},
};
#ifdef GDEBUG
# define gprintk( x... ) printk( x )
#else
# define gprintk( x... )
#endif
/* NAND parititon from 2.4.18-swl5 */
static struct mtd_partition miop550_nand_part[] = {
[0] = {
.name = "Boot Internal",
.size = SZ_1M,
.offset = 0,
},
[1] = {
.name = "S3C2410 flash partition 1",
.offset = 0,
.size = SZ_32M,
},
[2] = {
.name = "S3C2410 flash partition 2",
.offset = SZ_128M,
.size = SZ_32M,
},
[3] = {
.name = "S3C2410 flash partition 3",
.offset = SZ_128M * 2,
.size = SZ_32M,
},
[4] = {
.name = "S3C2410 flash partition 4",
.offset = SZ_128M * 3,
.size = SZ_32M,
},
[5] = {
.name = "S3C2410 flash partition 5",
.offset = SZ_128M * 4,
.size = SZ_32M,
},
[6] = {
.name = "S3C2410 flash partition 6",
.offset = SZ_128M * 5,
.size = SZ_32M,
},
[7] = {
.name = "S3C2410 flash partition 7",
.offset = SZ_128M * 6,
.size = SZ_64M,
}
};
static struct s3c2410_nand_set miop550_nand_sets[] = {
[0] = {
.name = "NAND",
.nr_chips = 1,
.nr_partitions = ARRAY_SIZE(miop550_nand_part),
.partitions = miop550_nand_part,
},
};
Is correct the code?
thnks.
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Received on Tue Aug 14 2007 - 09:43:04 EDT
This archive was generated by hypermail 2.2.0 : Tue Aug 14 2007 - 09:43:21 EDT