Re: [iPAQ] Ipaq Pcmcia 2fast4you ?

On Tuesday, April 17, 2001, at 04:03 PM, Nicolas Pitre wrote:

> Someone needs to review the PCMCIA timing initialization in
> drivers/pcmcia/sa1100-generic.c.

The socket driver initializes the MECR to the PCMCIA-spec timings (255ns
for I/O, 300ns for attribute and common memory) using the BS calculation
given in the SA-1110 manual. Note that the initialization occurs after
cpu-scale has had its chance to fiddle with, say, the PPCR. The MECR
values can change if Card Services requests new timings, but this is
uncommon.

The last time I heard a symptom that was anything like the one being
described, it involved a misconfiguration of the Assabet bus
transceivers when using Neponset. If there were a general timing setup
bug, I would expect to hear more complaints on various StrongARM
implementations.

Now, once a core clock change occurs at runtime, all bets are off. The
MECR values need to be recomputed based on the current PPCR value and
the desired cycle timings for each region of the PCMCIA space. This
information is all being kept in the socket driver, and it is a
straightforward proposition to trigger the update during a core clock
adjustment:

   ftp://ftp.wearablegroup.org/pub/software/patches/
     linux-2.4.3-rmk1-np1-jd1.patch.gz

I've been able to maintain access to a Microdrive using a variety of
/proc/scale values.

-jd
Received on Tue Apr 17 15:48:01 2001