Re: [iPAQ] more button problem info and O/C

>
> Yes, it does save battery power when the CPU speed is lowered. And in
> theory the voltage to CPU could also be adjusted down for further power savings
> (although I'm not sure how to do this on the iPAQ).
> I have just released a patch on the sa1100-linux@pa.dec.com list that should
> enable the bidirectional clock scaling work on the iPAQ (plus it does the
> appropriate recalibration of the kernel's timing code (loops_per_sec kernel
> variable). I did note that the iPAQ initially boots linux at 191.7 MHz instead
> of the 206 MHz I expected.

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How does this code differ from the clock scaling code in the Itsy distribution?
That version also has driver callbacks so that device drivers can shutdown
and restart following a clock change. This would be a good thing to mandate,
although it was not always necessary.
We used that version of clock scaling with a modified Itsy motherboard that
had two levels of voltage scaling (1.5 and 1.23V to the CPU). We had small
energy savings using voltage scaling, but the chip wasn't designed for that.
The "safe" speed at which to run varies from chip to chip. AFAIK, there is no
provision for multiple voltages in the iPAQ. I can send you a paper that will
appear in OSDI with the results of our experiments with this. In the absence of
other existing infrastructure that uses clock/voltage scaling, I would like to
maintain compability with the Itsy version.
The SA-2 architecture supports voltage scaling. The SA-2 core (what
would be equivilent to the SA-110) allegedly scales from 600Mhz to 150Mhz
and power goes from 450mw to 40mw across that range. Once you account
for clock scaling, this is a ~3x energy reduction.