Re: [iPAQ] cpu speed

Sonny Mounicou wrote:
> In digging throught the kernel code, I found how clockable this cpu
> is. I also found that the speed was defaulting to 192 MHz instead of
> 206 MHz.
>
> On line 340, I found in arch/arm/kernel/scale.c:
> static const scale_platform_data_t bitsy_platform_data =
> {
> 1,
> 9, /* Default speed: 191.7 MHz */
> 12, /* Speed limit: 235.9 MHz - heard rumor YMMV */
> sa11x0_3_6864_speeds,
> { bitsy_freq_regs }
> };
>
> Looking at the code, we can change the 9 to a 10 and this would give us
> our 206 MHz.

The default speed specified there is for reference only, and it corresponds
to the clock speed set by the iPAQ bootldr code. The clock scaling module
does not set the speed without user intervention. I would prefer that the
default value in scale.c was kept in sync with that set in bootldr. So
when the Compaq folks modify the value for bootldr, it should get
propagated to scale.c as well.

The bigest issue with overclocking the iPAQ is the type of SDRAM used.
From my understanding it is only rated at 100MHz, but was cherry picked by
Compaq because it could safely run at 103.2 MHz (206.4 MHz CPUClk/2 =
MemClk). When I added support for iPAQ to scale.c I was able to bring
some, but not all, iPAQ's up to 250.7MHz using the memory parameters listed
in scale.c, but that required setting the RAM clock speed down to MemClk/2
which is MemClk/4 (so at 250.7MHz the RAM is at 62.675 MHz). For some
iPAQ's it appears the memory isn't the only gating factor to speed. I've
been able to get some, but once again not all, hardware hacked iPAQs
(upgraded to 64MB w/ 133MHz CL=3 SDRAM) to run at up to 265.4 MHz with the
RAM running at MemClk (CPUClk/2) and appropriate timing parameters for the
memory chips in question. Although certain features like video and
CF/PCMCIA didn't work due to their timings not being adjusted to work at
the new speed.

A generalized hooking mechanism should probably be added to scale.c so that
other drivers that need to adjust timing parameters can do so, including
PCMCIA and video drivers.

There are two major open issues with the clock scaling support in scale.c
on the iPAQ, that don't exist on the Intel Assabet board:
1. If you go to speed 0 the iPAQ frequently locks up.
2. If you try to do too large a speed increment in one step (say from 73.7
MHz to 206MHz) you may experience a lockup (Your Mileage May Vary), but I
havn't had trouble doing that type of change in two steps (say from 1 =
73.7MHz to 7 = 162.2MHz, and then transition to 10 = 206MHz).

Any clues/fixed to those two problems would be good.
Discussion of what type of API should be setup to allow other drivers to
register for notifications before/after speed modifications would be
helpful.

Enjoy,
Erik Bunce
Received on Fri Oct 13 12:52:10 2000