RE: [iPAQ] 16-bit SRAM access on ipaq expansion pack(small correction)

Make sure that gcc is generating code for ARMV4. IIRC, ARMV3 did not
support halfword instructions.

Jamey

> -----Original Message-----
> From: Prabhat Avasare [mailto:avasare@imec.be]
> Sent: Sunday, February 03, 2002 10:21 AM
> To: ipaq@handhelds.org
> Subject: [iPAQ] 16-bit SRAM access on ipaq expansion pack(small
> correction)
>
>
>
> Hi.
>
> Just a small correction in my previous email
> (indicated by ^^). Sorry for that.
>
> best wishes,
> -- prabhat
> -----------------------------------------------------
> Prabhat Avasare avasare@imec.be
> Fri, 01 Feb 2002 19:54:30 +0100
>
> Hi.
>
> In our expansion pack for ipaq 3760, we were trying
> to do a simple SRAM access on MCS2 for 16-bit data.
> There were two problems with that :-
>
> 1. If we try to access expansion pack memory as
> (unsigned short*) in our C program(like
> *((unsigned short*)(EXAPNSION_MEM_BASE)) = 0x1234;),
> ^^
> arm-linux-gcc converts it into two instructions
> (hence more cycles) of STRB(byte store) each.
> For (int*) though, only one STR instruction is
> generated. Is this normal or are we missing something?
>
> 2. When connected to logic analyser we see that,
> in case of (int*) access, only D15-8 are filled
> with correct values, but D7-0 are all zeroes.
> I read in sa1100 developer's manual that nCAS[3-0]
> enable corresponding bytes during memory accesses.
> Has that got anything to do with this? If yes,
> how do I turn nCAS[] on?
>
> Best wishes,
> -- prabhat
> -------------------------------------------------------
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Received on Sun Feb 3 15:01:04 2002