Re: Re: [H2200-port] MMC/SD now works on h2200

Matthew Reimer wrote:

>On Wednesday 27 April 2005 01:21 am, Phil Blundell wrote:
>
>
>>On Tue, 2005-04-26 at 17:27 -0700, Matthew Reimer wrote:
>>
>>
>>>Yeah, it definitely wouldn't be worth it in that case. But I thought that
>>>DREQ just needed to stay high for the duration of the entire transfer,
>>>and therefore we'd only need to spin waiting for the initial data to
>>>become ready, set DREQEN, and then go off about our business while DMA
>>>takes care of the rest, disabling DREQEN when we get an RFLast interrupt.
>>>Is that not the case?
>>>
>>>
>>I don't think this will work. Since the DMA controller can read data
>>out of the HAMCOP many times faster than it is arriving from the card,
>>the FIFO will very quickly become empty. Once that happens, the DMA
>>controller must be immediately stopped, otherwise it will continue to
>>read garbage from the SDIDATA register and corruption will result.
>>Then, when more data arrives, the DMA controller must be re-started
>>quickly enough to prevent the FIFO from overflowing.
>>
>>Normally you'd solve this problem by connecting DREQ to the the "fifo is
>>not empty" signal. That way, when all the data has been consumed, DREQ
>>will go false and DMA transfers will stop. But that signal is not
>>available outside the HAMCOP, so this won't work in our case.
>>
>>Am I misunderstanding your suggestion?
>>
>>
>
>No, you're understanding my suggestion perfectly; I think I haven't properly
>understood how DMA/DREQ/DACK are meant to operate. It sounds like it's used
>for flow control, whereas I thought DREQ was just a signal to the DMA
>controller to start its transfer. So DREQ/DACK function like CTS/RTS?
>
>
No, DREQ is just a signal that inform the DMA that data is ready on its
source FIFO.
1) fifo has data --> DREQ is asserted
2) DMA read the data and DACK is asserted --> DREQ remain asserted if
and only if there is still some data in the fifo.

-- 
Pierre Tardy