From: George G. Davis (davis_g@mvista.com)
Date: Fri Oct 05 2001 - 18:44:15 EDT
Greetings,
Here's a fix for the standalone Assabet UDA1341 panics folks
have been reporting lately. This works for me. Although YMMV! : )
BTW, the InitMem algoithm doesn't work correctly on Assabet.
It always reports 64MB available when, in fact, there's only
32MB. I suspect using 16MB as the alias test for the 64MB
memory test isn't valid in this case.
N.B. Many folks have "MDCNFG_BANK0_ENABLE" turned on for their
target's "dram_mdcnfg_xxmb" constants. Bad idea! AFAICS, the
enabled banks should be defined via "dram_mdcnfg_enable". This
value is used to "turn-on" enabled banks only after the SDRAM
init is done with banks disabled (as per the SA-1110 dev man).
In other words, some targets may not be properly initing
the SDRAMS since they already have the banks enabled. Comprende?
Without futher adieu...
--- bootldr-2.14.15-jd1.orig/boot-sa1100.s Fri Aug 31 16:03:36 2001
+++ bootldr-2.14.15-jd1/boot-sa1100.s Fri Oct 5 14:20:41 2001
@@ -1981,17 +1981,24 @@
.align 4
dram_mdcnfg_64mbX: /* DRAM Configuration [1] 10.2 */
+#if !defined(CONFIG_ASSABET)
.long (MDCNFG_BANK0_ENABLE| MDCNFG_DTIM0_SDRAM | MDCNFG_DWID0_32B \
| MDCNFG_DRAC0(6) | MDCNFG_TRP0(3) | MDCNFG_TDL0(3) | MDCNFG_TWR0(3))
+#endif /* !defined(CONFIG_ASSABET) */
dram_mdcnfg_32mb: /* DRAM Configuration [1] 10.2 */
/* Bitsy development board uses two banks? KM416S4030C, 12 row address bits, 8 col address bits */
/* Bitsy uses two banks KM416S8030C, 12 row address bits, 9 col address bits */
/* Have to set DRAC0 to 14 row bits or else you only get 8 col bits */
/* read from the formfactor unit configuration registers: 0xF3536257 */
-#if defined(CONFIG_JORNADA720) || defined(CONFIG_ASSABET)
+#if defined(CONFIG_JORNADA720)
.long (MDCNFG_BANK0_ENABLE | MDCNFG_DTIM0_SDRAM | MDCNFG_DWID0_32B \
| MDCNFG_DRAC0(5) | MDCNFG_TRP0(2) | MDCNFG_TDL0(3) | MDCNFG_TWR0(1))
+#elif defined(CONFIG_ASSABET)
+ .long (MDCNFG_DTIM0_SDRAM | MDCNFG_DWID0_32B | MDCNFG_DRAC0(5) \
+ | MDCNFG_TRP0(2) | MDCNFG_TDL0(3) | MDCNFG_TWR0(1)) \
+ | ((MDCNFG_DTIM0_SDRAM | MDCNFG_DWID0_32B | MDCNFG_DRAC0(5) | \
+ | MDCNFG_TRP0(2) | MDCNFG_TDL0(3) | MDCNFG_TWR0(1)) << 16)
#else
.long (MDCNFG_BANK0_ENABLE | MDCNFG_DTIM0_SDRAM | MDCNFG_DWID0_32B \
| MDCNFG_DRAC0(5) | MDCNFG_TRP0(3) | MDCNFG_TDL0(3) | MDCNFG_TWR0(3))
@@ -2032,6 +2039,9 @@
#elif defined(CONFIG_SPOT)
.long (MDREFR_TRASR(1) | MDREFR_DRI(768) | MDREFR_E1PIN | \
MDREFR_K1RUN | MDREFR_K2RUN)
+#elif defined(CONFIG_ASSABET)
+ .long MDREFR_TRASR(7) | MDREFR_DRI(50) | MDREFR_K0DB2 | \
+ MDREFR_E1PIN | MDREFR_K1RUN | MDREFR_K2DB2
#else
.long (MDREFR_TRASR(1) | MDREFR_DRI(512) | MDREFR_E1PIN | MDREFR_K1RUN)
#endif /* CONFIG_JORNADA720) */
-- Regards, George
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